In many areas of the electronics industry, electronic circuit designers are turning toward the use of lower supply voltages. This approach enables circuit designers to design electronic systems with smaller power supplies, which may reduce product weight and size.
It is well known in the field of integrated circuits that the design of bias circuitry internal to a chip is essential because it determines the internal voltage and current levels of all operating conditions of the integrated circuit as well as manufacturing process variations. The industry trend for electronic systems encompassing operational amplifiers is also evolving toward lower supply voltages. Thus, amplifiers are used in applications requiring low voltage supply operations in addition to traditionally desired operational amplifier properties such as high input impedance, low input offset voltage, low noise, high bandwidth, high speed, and sufficient output drive capabilities.
Complementary metal oxide semiconductor (CMOS) differential amplifiers are used in both analog and digital circuits. Conventional configurations of CMOS operational amplifiers include a CMOS differential amplifier having a differential input stage followed by an output stage. It is well known in the art for a CMOS operational amplifier to include a CMOS differential input stage and a class AB output stage.
FIG. 1 is a circuit diagram of a conventional CMOS amplifier 100. Amplifier 100 includes a differential input stage 102 and a class AB output stage 108. Input stage 102 includes a positive input terminal 110, a negative input terminal 12, and a current source 114 operably coupled to the source of transistor M31 and the source of transistor M32. Furthermore, input stage 102 includes a summing circuit (transistors M20, M21, and M23-M28) and a floating current source (transistors M29-M30 and transistors M3 and M4 which are connected in a common gate configuration). Output stage 108 includes bias circuit 106 and an amplifier output 120. Amplifier output 120 is operably coupled between the drains of transistors M1 and M2 with the source of transistor M2 operably coupled to a ground voltage Vss. Furthermore, the source of transistor M1 is operably coupled to a voltage supply Vaa.
Bias circuit 106 includes stacked diode-connected transistor branches 140 and 142 that include stacked diode-connected transistors M9 and M8 and stacked diode-connected transistors M5 and M6, respectively. The source of transistor M9 is connected to voltage supply Vaa and the source of transistor M5 is connected to ground voltage Vss. Furthermore, the drains of each transistor M6 and M8 are connected to current sources 118 and 116, respectively. The output transistor quiescent current IQ is mirrored from the stacked diode-connected transistors M9/M8 and M5/M6 through the common-gate-connected transistors M3 and M4. At a quiescent operating point, complementary currents I1 and I2 are equal and the drains of diode-connected transistor M6 and M8 are used to bias the gates of transistors M4 and M3, respectively.
As configured, conventional CMOS amplifier 100 requires, at a minimum, a supply voltage that is equal to the voltage needed to bias each stacked diode-connected transistor branch 140, 142. Stated another way, in order to bias common-gate-connected transistors M3 and M4, voltage supply Vaa must be at least equal to the gate-to-source voltage drop across two stacked transistors (2Vgs), such as transistors M9 and M8 or transistors M6 and M5. As a result, conventional CMOS amplifier 100 requires a supply voltage that is greater than the minimum supply voltage of conventional output stages within CMOS amplifiers.
There is a need for methods, apparatuses, and systems to decrease the required supply voltage of an operational amplifier. Specifically, there is a need for dynamic bias control circuit to enable low voltage operation of an operational amplifier.